The present invention relates to a process for planarizing a surface layer of a semiconductor device in a system for producing the semiconductor device, and more particularly to a process for planarizing a trench element isolation region thereof.
In manufacturing a semiconductor device, inevitable wires on an interlayer insulating layer are formed, by forming isolation regions of, for example, LOCOS structure or wires on the semiconductor substrate, forming wires on the isolation regions, or forming interlayer insulating layers on the semiconductor substrate. By the wires, isolation regions or the like, remarkable corrugations or convex/concave portions are formed on a surface of the semiconductor substrate on which wires or the like are formed, the interlayer insulating layers on which the wires or the like are formed, the semiconductor substrate on which the isolation regions of LOCOS structure are formed, the semiconductor substrate or the like having wires or the like formed on the isolation regions of LOCOS structure (hereinafter generally referred to as a semiconductor intermediate product). As a result, a height of the surface of the semiconductor intermediate product is locally changed and not plain.
In accordance with the micro-miniaturization tendency in device size of semiconductor integrated circuits, the wavelength of exposure radiation sources used for lithography has become shorter and shorter. An exposure depth of focus is in proportion to an inverse number of the wavelength. As a result, the exposure depth of focus has become shorter and shorter. Accordingly, if remarkable unevenness or corrugation is present on a surface of an intermediate product of the semiconductor device when a photoresist is applied to the surface of the intermediate product of the semiconductor device and the photoresist is exposed, the height of the surface of an integrated circuit locally varies, the exposure position of the photoresist from a projection optical system would not fall within the optimum exposure depth of focus of the projection optical system. As a result, there would be a problem that a line width of the photoresist pattern on the intermediate product of the semiconductor device obtained by carrying out exposure and development of the photoresist would locally vary in the intermediate product of the semiconductor device. Alternatively, there would be another problem a that a configuration of the photoresist pattern is displaced or offset from a desired configuration.
Furthermore, when an interconnection layer is to be formed over an interlayer insulating layer, if remarkable corrugations are present on the surface of the interlayer insulating layer, a local variation in thickness of layer would occur in the interconnection layer. If such an interconnection layer is patterned into a desired configuration, the interconnections made from a thin part of the interconnection layer would be thinned and a breakdown voltage of interconnections formed from a thin interconnection layer would be reduced.
Recently, various techniques have been studied and proposed in which formation of corrugations is avoided on the surface of the intermediate product of the semiconductor device as much as possible. Of these techniques, there are proposed, a borophosphosilicate glass (BPSG) reflow method, an insulating layer accumulation etch-back method, an SOG (Spin On Glass) smoothing method, a method wherein surface convex portions are positively etched for planarization, and a planarizing technique that uses polishing.
An outline of the polishing planarizing technique will be explained below with reference to FIGS. 24A to 24D, which show manufacturing steps.
As shown in FIG. 24A, interconnections 114 are formed on an upper surface of a semiconductor substrate 110. An insulating layer 121 made of silicon oxide is formed on the upper surface of such as a silicon substrate 110 by, for example, a CVD method (see FIG. 24B). Next, as shown in FIG. 24C, the upper surface of the insulating layer 121 is polished to planarize the surface thereof.
On the other hand, the LOCOS method has been conventionally used as an isolation region forming method for the semiconductor device. In the LOCOS method, the silicon semiconductor substrate is selectively thermally oxidized by using a silicon nitride layer as a mask to form an isolation region made of an oxidized layer on the silicon semiconductor substrate. However, upon the thermal oxidization, a so-called birdbeak phenomenon would occur in which the oxidization layer is developed in the horizontal direction of the silicon semiconductor substrate from edge portions of the silicon nitride layer toward the silicon layer. As a result, a conversion difference between a designed mask and a pattern of an actual element separation region would be caused so that it would be difficult to meet a requirement of the micro-miniaturization of the semiconductor elements.
In order to cope with such a problem, a so-called trench element isolation region forming method has been proposed in which trench portions (trenches) are provided on the semiconductor substrate by reactive ion-etching or the like and insulating layers are filled in the trench portions. In the trench element isolation region forming method, after the trench portions (trenches) have been formed in the semiconductor substrate, the insulating layer is accumulated on the surface of the semiconductor substrate as well as the interiors of the trench portions, and the insulating layer is etched back by the reactive ion-etching so that the upper surface of the semiconductor substrate is again exposed while leaving the insulating layers within the trench portions. For example, semiconductor elements are formed on the exposed parts of the semiconductor substrate.
The most significant problem of the conventional trench element isolation region forming method resides in a planarizing method of the insulating layer. Namely, the trench element isolation region forming method based upon such an etch-back technique suffers from a problem that, when the insulating layer is etched back, no insulating layer is left within the trench portion which is large in width for forming a wide field region. Accordingly, in the method using such an etch-back technique, the LOCOS method has to be used together. More specifically, the isolation region is formed for the narrow trench portion by the trench element isolation region forming method, whereas the isolation region (wide field region) is formed for the wide trench portion by the LOCOS method. In such an isolation forming method which requires both the LOCOS method and trench element isolation region forming method, the number of steps is increased and the work is complicated. Therefore, this method is unsuitable for the mass-production of semiconductor devices.
On the other hand, typical planarizing methods in which the amount of the left insulating layer would hardly be changed depending upon a width of the portion where the isolation region is to be formed and in which all the isolation regions may be formed only by the trench element isolation region forming method are, for example, a chemical mechanical polishing method (CMP method), a mechanical polishing method and the like. According to the trench element isolation region forming method based upon the CMP method or the like, it is possible to form a wide element isolation region having a width of 10 .mu.m to 1,000 .mu.m (i.e., wide field region) and to considerably reduce the isolation region forming steps. Accordingly, the CMP method or mechanical polishing method has recently been noticed as a trench element isolation region forming method which is the most contributable to the productability.
However, the above-described planarizing method that uses the BPSG reflow method, the insulating layer deposition etch-back method or the SOG smoothing method allows unevenness to be only locally suppressed. Therefore, the conventional method cannot solve the above-described problems in terms of photolithography. The method wherein the surface is planarized by positively etching projections on the surface involves the problems that the etch rate must be controlled and that the number of process steps increases.
With the corrugation smoothing method that uses the polishing planarizing technique, when the insulating layer 121 is polished, the polishing rate or the polishing amount of the insulating layer 121 in a surface of a single wafer (hereinafter simply referred to as a wafer surface) is not uniform. As a result, as shown in FIG. 24C, the layer thickness of the polished insulating layer 121 becomes nonuniform in the wafer surface and further in the semiconductor device intermediate product. Accordingly, the photolithography problems cannot be solved by this method, either. Furthermore, to form connecting holes such as via-holes in the insulating layer 121 above the interconnections 114, it is necessary to form openings in the insulating layer 121 above the interconnections 114 (see FIG. 24D). In the case where the layer thickness of the insulating layer 121 above each interconnection 114 varies, it is necessary to increase the etch rate for the portions of the insulating layer 121 where the layer thickness is relatively large. The method involves a problem that the etching condition of the insulating layer 121 becomes complicated. Also, in a polishing process in which a polishing rate is not kept constant, since the polishing amount depends upon the variation of the polishing rate, it is very difficult to control the layer thickness of the insulating layer 121 after polishing.
The conventional trench element isolation forming method using the CMP method or mechanical polishing method suffers from two problems. Namely, it involves one problem that the semiconductor substrate including the isolation region formed by polishing would be damaged (see FIG. 25A which is a schematic view) and the other problem of uniformness in polishing in the wafer surface. If the damage is generated in the element isolation region, the breakdown voltage of the isolation region is reduced. Also, if the damage is generated in the semiconductor substrate, when the semiconductor element is formed in the region of the semiconductor substrate, for example, a leak current of the semiconductor element is increased. Incidentally, in FIG. 25A, reference numeral 110 denotes the semiconductor substrate, numeral 130 denotes a bottom portion (recess) of a stepped portion formed in the semiconductor substrate, numeral 141 denotes the insulating layer formed of, for example, SiO.sub.2, and numeral 131 denotes the isolation region.
Damage to the semiconductor substrate may be improved to some extent by sacrificing polishing rate or flatness of the insulating layer 141. More specifically, if, for instance, a colloidal silica where a secondary particle diameter of polishing powder used in the CMP method is reduced to a small value (about 10 nm or less) is used, and a piece of polishing cloth having a low hardness as a piece of polishing cloth (about 70 to 80 in terms of Asker-C hardness) is used, it is possible to suppress the damage to the semiconductor substrate. However, in this case, the polishing rate is low (about 10 nm/min or less), and the amount of removal of convex portions relative to the polishing amount is also small. Accordingly, it takes two hours or more to polish a piece of wafer, and hence, the through-put is extremely low. If the wafer has a large aperture, there is a problem in uniformity of polishing within the wafer. As a result, it is difficult to simultaneously process a plurality of pieces of wafer. Accordingly, it is not practical to solve the problem of damage to the semiconductor substrate by such a method.
In the case of selectively removing the insulating layer by a CMP method, the insulating layer is removed by both chemical reaction of the insulating layer with the polishing liquid and mechanical polishing of the insulating layer by the polishing material. Therefore, in order to solve the problem of the generation of the damage in the semiconductor substrate according to another method, it is possible to use a method for enhancing the chemical polishing characteristics by the CMP method. Namely, there is a method in which a silicon oxide layer or a polycrystalline silicon layer containing impurities is accumulated to form the insulating layer and the latter layer is planarized by the CMP method. The polishing of the insulating layer is developed by the chemical reaction between the impurities contained in the insulating layer and the polishing liquid. Therefore, damage to the semiconductor substrate is reduced, and the polishing rate is relatively high at about 100 nm/min. Accordingly, there is no problem in through-put.
However, the above-described approach suffers from a problem in which, since the polishing of the insulating layer is isotropically developed by enhancing the chemical polishing property, the layer thickness of the wide bottom portion (recess) of the stepped portion is reduced (so-called dishing). This phenomenon is schematically shown in FIGS. 25B and 25C. Incidentally, in FIG. 25B, the position of the surface of the insulating layer 141 which is being polished is indicated by the dotted line.
On the other hand, the problems of non-uniformity in the wafer surface involves two causes. Once cause is a distribution (gradient) of the accumulation layer thickness of the insulating layer in the wafer surface, and the other cause is a distribution (gradient) of the polishing rate in the wafer surface. In a current insulating layer accumulation apparatus (for example, CVD apparatus) for processing wafers having a diameter of 8 inches, the distribution (gradient) of the accumulation layer thickness of the insulating layer in the wafer surface is .+-.3 to 5%. On the other hand, the current chemical mechanical polishing apparatus for processing wafers having a diameter of 8 inches, the polishing rate within the wafer surface is varied in the range of at least about .+-.3 to 5%.
Accordingly, if these variations are added, the polishing uniformity within the wafer surface is varied in the range of at least .+-.3 to 5%. In the conventional trench element isolation region forming method, since the insulating layer is made of a kind of material, the polishing or cutting amount of the insulating layer in the wide bottom portion (recess) of the stepped portion formed in the semiconductor substrate is increased. Accordingly, in order to positively leave the insulating layer within the wide bottom portion and to planarize the insulating layer as much as possible, it is necessary to select the thickness of the insulating layer to be accumulated to a height which is approximately twice larger than that of the stepped portion. For instance, if the height of the stepped portion is 0.5 .mu.m, the thickness of the insulating layer to be accumulated is about 1 .mu.m, and the polishing uniformity in the wafer surface is varied in the range of at least .+-.50 to 100 nm.
Japanese Patent Application Laid-Open No. Sho 59-136943 discloses an isolation region forming method in which the insulating layer which has a thickness that is at least greater than a depth of the groove is accumulated over the entire surface, and thereafter, such an insulating layer is removed by the CMP method. However, in the technique disclosed in this publication, the insulating layer is basically formed of a kind of material or two insulating films each of which is made of material having substantially the same polishing rate. Accordingly, it is difficult to solve the dishing phenomenon problem. Also, since the insulating layer having a thickness greater than the depth of the groove is accumulated over the entire surface, the polishing uniformity within the wafer surface would be degraded.